RISC-V Summit Europe 2026
2026-06-08..2026-06-12
Bologna, Italy
[RISC-V Summit Europe 2023, RISC-V Summit Europe 2024, RISC-V Summit Europe 2025, RISC-V Summit Europe 2026, RISC-V Summit Europe 2026 Developer Workshops]
| title | author | length |
|---|---|---|
| RISC-V Custom Instructions for Automotive Control and DSP Algorithms Compliant with ISO 26262 | Sai Swaroop Maram, Johannes Sanwald, Andreas Mauderer, Jan-Hendrik Oetjens, David Higham, Maricel Ventura, Zdenek Prikryl | 15m |
Claim: Codasip and Bosch demonstrate a bounded customization flow that keeps ISO 26262 compliance while adding RISC‑V custom instructions via Codasip Studio to… | ||
| Nuclei: Full-Spectrum RISC-V IP & Automated SoC Design from Months to Hours | Bob Hu | 18m |
Company claims an industrial flow that automates SoC composition from months to hours using a GUI Subsystem Architect where designers drag CPUs, buses, SRAM… | ||
| CPU Utilization Counters for RISC-V | Esther Zhang | 15m |
Proposal adds two CSRs: a core-cycle counter that increments at actual CPU frequency and an active-time counter that ticks at a fixed reference rate, both stop… | ||
| Ultra Low Power RISC-V Core Retention with Warm Restart Extension | Anne Merlande | 15m |
SXP5 RISC‑V core adds a retention domain and a tightly coupled retention stack in TCM plus a retention request protocol to save full CPU context and CSRs… | ||
| An Open-Source CVA6S+ High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs | R. Tedeschi | 14m |
An open-source CVA6S+ cluster implements AMBA 4 ACE coherence with a new CCU IP and a snoop fabric using snoop-based MOESI to move dirty L1 lines, targeting… | ||
| Accelerating RISC-V Innovation with openMPACT Tools from Google | Yenkai Wang, Tor Jeremiassen, Julian Mullings-Black | 17m |
Google Research provides Impact Sim — an ISA-description-driven C++ simulator SDK that claims a simple core up in under a week and generates… | ||
| SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification | Yinan Xu | 14m |
Claims a synthesizable reference model that moves the golden ISA into hardware, generated by a semantic migration tool from Spike to chisel primitives, and… | ||
| RIVIERAA Programmable RISC V Edge Architecture | Luca Lingardo, Tiberio Fanti | 14m |
NXP develops RIVIERA, a RISC-V edge architecture for NFC that moves DSP tasks to a microprocessor plus tightly coupled hardware accelerator using the ISA… | ||
| RVEdge-Vision: A Fully Open,Ultra-Efficient On-Device AI Platform for Smart Eyewear | Michele Magno | 16m |
An open prototype integrates a Gap9 RISC‑V SoC, an ultra‑low‑power RGB DAX036X and an event‑based GenX320 camera, plus BLE, mic and speakers, inside a glasses… | ||
| ARBEL™ The Leading Server-Class RISC-V CPU | Yiftach Gilad | 15m |
Next Silicon shows working silicon and a roadmap: test chip: dual‑core 2.4 GHz with PCIe CXL and PCIe Gen5 IO, 2 MB L3 per home node, runs Ubuntu and GCC/LLVM… | ||
| Enabling High-Performance Storage for RISC-V | Dave Cremins, Abdul Halim | 15m |
Lustre client ported to RISC-V by adding architecture support and three core changes (build target, 64-bit erasure coding paths, fallback header) and landing 7… | ||
| Transforming MCUs in an AI-Defined Era | Edward Wilford | 18m |
Argues that automotive compute shifts gradually from ~130 discrete ECUs toward hybrid zonal architectures rather than a single central box, cites OEM… | ||
| Panel: Realising the Future of European Computing from Research to Industry | Philipp Tomsich, Georgi Kuzmanov, Sachiko Muto, Fabien Piuzzi, Enrico Sangiorgi, Edward Wilford | 53m |
Europe has a draft Chips Act 2 draft that shifts from money-on-the-table to creating demand, pilot lines and a network of competence centers for training; open… | ||
| Matrix Extensions for RISC-VDelivering on the Promise | Philipp Tomsich | 22m |
RISC-V standardization splits matrix support into four concrete ISAs: a dot product fast track already through internal review, an IME that uses no new state… | ||
| From Eyewear to Silicon: RISC-V for Low-Power AI in Next-Generation Smart Glasses | Marco Fariselli | 30m |
Luxottica builds a RISC‑V based SoC using the PULP ecosystem plus custom IP to hit sub‑35 mW system budgets for 150 mAh glasses running 16 hours. ISA… | ||
| RISC-V: Enabling Open Physical AI | Luca Benini | 30m |
Argues RISC-V hardware and software enable practical “physical AI” by combining ISA extensions, tightly coupled accelerators and large latency-tolerant… | ||
| State of the Union | Krste Asanovic | 32m |
State of RISC‑V is strong: RVA23 ratified Oct 2024 and vendor silicon appears in 2026, under a ratified server platform spec, but parity with incumbents needs… | ||
| nothing matches | ||