Harvesting Sub-Microsecond CXL Memory Stalls with LiteSwitch
Talkat 20th USENIX Symposium on Operating Systems Design and Implementation (OSDI '26) · 2026-07-13..07-15·
summary
LiteSwitch is a hardware–software co‑design that harvests sub‑microsecond CXL memory stalls by detecting CXL‑bound loads on the memory path and redirecting control in ~20 ns, then switching to another ready thread in under 20 ns. It implements LDMBB detection in hardware, a user‑space handler plus bundle handoff for 4 ns scavenger selection, and Xsave/Xrestore skipping using an offline X‑free function map. Emulated with Intel PMU and a Kadona user‑thread runtime, it recovers up to 80% of CXL‑induced slowdown for stalls ≥200 ns.
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chapters (10)
- 0:00LiteSwitch and CXL stalls
- 1:02CPU memory stall problem
- 2:28Store harvesting importance
- 5:17LiteSwitch design insights
- 7:05Hardware: Location Dependent Memory Branching
- 8:31Software: Bundle handoff and context switching
- 10:18Context switch overhead with X-state analysis
- 13:45Evaluation setup and workloads
- 15:30Performance results and slowdown reduction
- 17:39Summary and future directions
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