RISC-V Summit Europe 2025
2025-05-12..2025-05-15
Paris, France
[RISC-V Summit Europe 2023, RISC-V Summit Europe 2024, RISC-V Summit Europe 2025, RISC-V Summit Europe 2026, RISC-V Summit Europe 2026 Developer Workshops]
| title | author | length |
|---|---|---|
| Open Source Chip Design in the European Semiconductor Strategy | Stefan Wallentowitz | 33m |
Europe now has an end-to-end open source chip: Basilisk SoC is taped out in IHP 130 nm BiCMOS, uses a CVA6 core, runs Linux and publishes GDS2 and RTL. The… | ||
| Going BIG With the RISC-V Ecosystem | Larry Wikelius | 17m |
RISC-V International reaches a 15th anniversary with 135 ratified extensions and a push from Qualcomm-backed work to move from an ISA to an… | ||
| Towards Open-Source and Automatic Performance Characterization Hardware | Matthew Edwin Weingarten, Tanvir Ahmed Khan | 16m |
Open-source RISC‑V cores lack the hardware hooks needed for reliable top‑down microarchitectural analysis, so an effort instruments RTL and expands event sets… | ||
| Efficient debug and trace of RISC-V systems: a hardware/software co-design approach | Oana Alexandra Lazar, Henrique Mendes, Angelo Maldonado-Liu | 16m |
A hardware/software co‑design called UltraSoC‑V ships preverified IP (E‑Trace–compliant enhanced trace encoder) that compresses trace to an average 0.2 bits… | ||
| Improvements to RISC-V Vector code generation in LLVM | Alex Bradbury, Luke Lau | 16m |
LLVM adds middle-end and backend changes for RVV including VL tail folding and non-power-of-two SLP support, a pass to reduce VL to demanded, and backend… | ||
| Fast and fine-grained compartmentalisation in CHERI | Franz A. Fuchs, Peter Rugg, Dapeng Gao, Jonathan Woodruff, Alexandre Joannou, Robert N. M. Watson, Simon W. Moore | 11m |
Demonstrates a CHERI-enabled out-of-order superscalar RISC-V core running CheriBSD on a DE10Pro FPGA, using 128-bit capabilities to enforce per-library stacks… | ||
| Developing Custom RISC-V ISA Extensions for General Embedded Image Processing Operations | Carsten Rolfes, Stephan Nolting | 09m |
An FPGA prototype connects a grayscale image sensor to a RISC-V ASIP that implements Custom RISC-V ISA extensions using single-instruction multiple-data (SIMD)… | ||
| “One Student One Chip" - Learn to Create Your Own RISC-V Processor From Scratch | Xiaoke Su, Zeyu Gao | 09m |
Third-generation SOC called StarrySky development board integrates multiple student-designed RISC-V cores selectable by a six-bit DIP switch, ships with… | ||
| Open-Source Xiangshan Nanhu Processor Experience Day | Haojin Tang, Xin Li, Xuan Hu, Xi Chen, Yinan Xu | 10m |
Second-generation Nanhu boards boot Linux and run video playback, web browsing and even GPU-backed cloud game streaming; hardware is on GitHub with 6.4k stars… | ||
| OmniXtend: Open Coherent Memory Fabric for RISC-V | Seung-Jun Cha, Hyuk Je Kwon, Young Woo Kim, Song-woo Sok, Jinmee Kim, Hag Young Kim, Kwang-Won Koh, Kang Ho Kim | 10m |
Open coherent memory fabric that runs coherent over Ethernet and uses an FPGA fabric controller talking to a RISC‑V SoC; demo runs random memory accesses… | ||
| RISC-V: Reaching New Orbits in Space Computing | Lucana Santos | 13m |
ESA reports a concrete roadmap: a RISC‑V SoC called GR765 targets tape-out Q4 this year with prototypes next year, integrating SIMD extensions for GNSS and AI… | ||
| Unleashing the Power of RISC-V E-Trace with a Highly Efficient Software Decoder | Marcel Zak, Mat O’Donnell, Vivek Chickermane | 17m |
Siemens EDA presents a software E-Trace decoder that reconstructs full instruction traces from a compressed on‑chip encoder, claiming up to 700x compression… | ||
| Challenge Accepted: Python Packaging Infrastructure for the RISCV64 Ecosystem | Trevor Gamblin, Mark D. Ryan, Julien Stephan | 12m |
Provides binaries for RISC‑V Python by building wheels in CI so pip finds them instead of compiling from source. The wheelbuilder project uses GitLab CI… | ||
| MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster | Sergio Mazzola, Yichao Zhang, Marco Bertuletti, Diyou Shen, Luca Benini | 13m |
MemPool presents three implemented RISC-V manycore flavors with measured trade-offs: MemPool scales to 1024 PEs via hierarchical tiles (4 cores/tile, 16… | ||
| Compared Analysis of GCC Codegen for AArch64 and RISC-V | Paul-Antoine Arras | 15m |
Collected SPEC CPU2017 dynamic instruction count data on a Banana Pi F3–class config using fixed GCC builds and user‑mode QEMU with a hotspot plugin, comparing… | ||
| Awards Ceremony | Andrea Gallo | 09m |
Ceremony presents the Ratification Award 2024–2025 to 14 contributors who drove concrete spec work: ratifying spec 1.13, the debug specification, conditional… | ||
| FGMT-RiscV running on an FPGA evaluation board with a live GDB debug session | Bernhard Lang | 11m |
A fine‑grained multithreading RISC‑V core runs on a Basis three board in an FPGA with a shared memory and Wishbone peripherals, a timer interrupt and… | ||
| Profiling Whisper AI Model on RISC-V: CPU, GPU, and NPU Performance on the DC-ROMA AI PC | Tan Siret AKINCI | 10m |
DC-ROMA RISC-V AI PC runs Whisper.cpp across CPU, GPU and an NPU prototype on an ESIN 7702 SoC with P550 cores and up to 50 TOPS at 1.8 GHz. CPU inference on… | ||
| Optimizing Sparse matrix-vector multiplication on the EPAC architecture | Davor Sluga, Ratko Pilipovi? | 09m |
Implementation targets the EPAC Vitruvius VPU emulated on the FPGA SDV at BSC-CNS and compares CSR/CCR and ALPaC-like formats using scatter/gather versus… | ||
| Spike-RTL: quasi-cycle accuracy hardware/software co-simulation | Raul Gomez-Varela, Hector Posadas, Eugenio Villar | 19m |
Spike-RTL replaces processor and memory Verilog with Spike and drives the rest of the platform under Verilator, demonstrated on a modified X-HEEP platform and… | ||
| A RISC-V Compatible Systolic Array for TinyML Applications in CFU Playground | Omar Mardini, Omar Shibli, Mazen Saghir | 14m |
A configurable RISC-V compatible systolic array is implemented in CFU Playground as a CFU co-processor and runs on an Arty A7-100T (Artix‑7) FPGA at 100 MHz. A… | ||
| METASAT Demonstrator: Mixed Criticality, Accelerated AI Computing for Future Space Systems | Marc Solé Bonet, Jannis Wolf, Matina Maria Trompouki, Leonidas Kosmidis | 06m |
A prototype SoC runs on an VCU118 FPGA and QEMU emulator combining a NOEL-V multicore with a custom SPARROW SIMD unit and a VORTEX GPU; three AI apps run in… | ||
| The Significance of the RVA23 Profile in Advancing RISC-V Ecosystem | Mark Hayter | 18m |
RVA23 standardizes a 64-bit application-processor ISA to guarantee user-space binary compatibility across RISC-V silicon, making vector and recent… | ||
| Panel – Enterprise Linux Enablement on RISC-V | Isaac Chute, Gordan Markuš, Jeffrey ‘Jefro’ Osier-Mixon, Gerald Pfeifer, Barna Ibrahim | 31m |
Major enterprise distros report concrete work: dedicated engineering teams, build infrastructure and community engagement; Open Build Service drives daily… | ||
| RISC-V open designs and contributions to hardware security research and development activities | Éric Saliba | 20m |
ANSSI describes concrete projects: an IPCC ECC hardware accelerator implements ECC with switchable side‑channel and fault countermeasures and runs on a SoC… | ||
| OpenTitan Integrated: A RISC-V Open-Source Silicon Root-of-Trust for large SoCs | Robert Schilling, Samuel Ortiz, Ravi Sahita, Andreas Kurth | 15m |
OpenTitan Integrated is an upstream, permissively licensed RISC-V silicon root-of-trust adapted for large SoCs with concrete additions: a mailbox interface… | ||
| Farewell and upcoming Summits | Teresa Cervero | 07m |
Summary of closing and future summits: this summit records 710 attendees from more than 40 countries, with 16% female representation and thanks to sponsors… | ||
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