RISC-V Summit Europe 2023
2023-06-05..2023-06-09
Barcelona, Spain
[RISC-V Summit Europe 2023, RISC-V Summit Europe 2024, RISC-V Summit Europe 2025, RISC-V Summit Europe 2026, RISC-V Summit Europe 2026 Developer Workshops]
| title | author | length |
|---|---|---|
| Opening | Calista Redmond | 27m |
RISC‑V claims concrete scale and momentum: more than 10 billion cores in market, over 11,000 engineers contributing, 70 active workgroups, seven ratified… | ||
| Welcome from the RISC-V Summit Europe Steering Committee | Christian Fabre | 05m |
Event planning and scope are explained: Barcelona is chosen, a steering committee merged three national meetups (Spain France Germany) and expanded to include… | ||
| RISC-V Summit Europe Program Overview | Daniel Müller-Gritschneder, Teresa Cervero | 05m |
Conference program presents concrete numbers and focus areas: 147 submissions, of which 19 technical talks, 8 industrial talks, 114 posters and 19 keynotes… | ||
| RISC-V: The Road Ahead and Technical Update | Mark I. Himelstein | 15m |
RISC-V reports scale (about 10 billion cores reported in 2021 and Qualcomm quietly shipping ~650 million Snapdragon cores) and a push from a mostly-Asia… | ||
| Commercial Adoption of CORE-V Open-Source RISC-V Cores - Lessons Learned | Rick O'Connor | 16m |
OpenHW’s CORE‑V family provides SystemVerilog RISC‑V cores with a UVM verification bench that runs on commercial EDA simulators and has 54 GitHub project… | ||
| Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive & More | Balaji Baktha | 19m |
Claims a RISC‑V 16‑core compute cluster with L1/L2/L3 caches and a coherent fabric that matches or beats incumbent single‑socket performance, delivered as a… | ||
| The RISC-V Verification Ecosystem with Open Standards and Commercial Tools | Jon Taylor | 15m |
RISC-V verification requires scaling beyond ad hoc tests to meet one quadrillion cycles of coverage estimated for modern CPUs, a number that RTL simulation at… | ||
| RISC-V customization, HW/SW co-optimization, and custom compute | Brett Cline | 11m |
Argues that adding custom instructions to RISC‑V yields both flexibility and fixed‑function performance, using a workflow that profiles actual software and… | ||
| RISC-V is Firing on All Cylinders | Charlie Su | 14m |
Company claims over 12 billion SoCs shipped and shows silicon and deployed systems: an X65 core hitting 2.4 GHz on 7 nm after fixes, a dual-issue X45 MPV… | ||
| HW-SW Interface for RAS in RISC-V Architectures | Daniele Rossi | 17m |
A hardware–software RAS interface for RISC-V implements memory error aggregation, logging and escalation with configurable feature and control registers… | ||
| Semidynamics Highly Configurable OOO Vector Unit | Roger Espasa | 16m |
Fully RVV1.0 compliant and offered in configurable sizes (start at 4, options up to 32 vector cores), the unit runs fully out-of-order vector renaming with… | ||
| RISC-V and Antmicro’s visual system designer: Everything everywhere all at once | Michael Gielda | 14m |
A visual system designer ties an open-component database, Renode simulator and Kenning + IREE ML toolchain to let users assemble RISC‑V cores, peripherals… | ||
| Enhancing the RISC-V Trace Encoder to Verify the Control-Flow and More | Anthony Zgheib | 15m |
Implements two verifiers: a standard-compliant verifier and an enhanced trace encoder on FPGA around an Ibex RISC‑V core; static tool generates metadata and a… | ||
| Enabling Virtualisation on RISC-V Microcontrollers | Stefano Mercogliano | 15m |
Proposal splits machine mode into EM/RM CSR replication so guests run in EM with redirected CSRs while RM holds originals and new controls, and adds a… | ||
| Mitigating Transient-Execution Attacks with CHERI Compartments | Franz Fuchs | 16m |
Reproduces six transient‑execution attacks (four Spectre variants plus two Meltdowns) on an out‑of‑order superscalar CHERI RISC‑V softcore and shows secrets… | ||
| Safe, Secure and Reliable Computing with the NOEL-V Processor | Jimmy Le Rhun | 14m |
De-RISC delivers a working NOEL-V on FPGA platform: a 4-core RV64GCH system with GPL/commercial cores, H-extension hypervisor support, PMPU/IOMMU isolation… | ||
| The RISC-V opportunity in Automotive Electronics | Franck Bernard | 37m |
Bosch positions RISC‑V as a candidate for a chiplet-based architecture that spans tiny sensor MCUs to centralized vehicle computers, targeting production-ready… | ||
| Developing a RISC-V Automotive Safety Island | Peter Lewin | 17m |
Proposes a physically isolated on-chip safety island that runs RISC-V real-time CPU cores in lockstep with ECC-protected TCMs, its own interconnect, clocks and… | ||
| What’s the Reality of RISC-V in Automotive? | Nitin Dahad, Andrew Frame, Travis Lanier, Peter Lewin, Charlie Su, Itai Yarom | 53m |
Panel asserts RISC-V is already moving into cars with some customers targeting mass production around Mobileye production 2025, and broader adoption stretching… | ||
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