Zephyr RTOS: Under 1KB of RAM
summary
Zephyr runs under 1 KB of SRAM by aggressively shrinking the data section and stacks: kernel footprint drops to ~128 bytes, final board image sits at ~892 bytes RAM used before toggling device to real 1 KB. Techniques include fake RAM in device tree to iterate builds, compiler flags (-Oz), west RAM/ROM/pcov reports and pole analysis, and runtime tricks like enabling heap briefly and stack canary measurement. Result: multitasking with UART/GPIO and working I2C target scans plus ADC transfers on TI MSPM0, with system timer implemented and sub-2 µA sleep.
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chapters (22)
- 0:00Introduction
- 1:04Current RAM usage
- 3:35Porting to MSPM0 CX
- 5:23Initial optimizations
- 7:10Low-hanging fruit
- 7:55Execute-in-place RAM
- 8:36Memory analysis tools
- 10:21RAM report limits
- 11:02RAM layout with report
- 13:07Data section variables
- 15:34Boot and thread init
- 17:22Dummy thread impact
- 18:49Remove dummy thread
- 21:59Final optimizations
- 22:41Debug hello world
- 23:46SysTick-less timer
- 25:29I2C under 1KB RAM
- 27:15Stack overflow analysis
- 29:00Stack canary method
- 31:12I2C scan optimizations
- 31:55Kernel optimizations
- 33:25Q&A
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