The Rockling FPGA Audio processor and Theremin SAO and Party Button SAO
summary
Rockling is a small UP5K FPGA board with about 5000 LUTs and 128 KB RAM that ships with an audio front end, an AD/DA codec, eight DSP blocks and a soft RISC‑V core; toolchain is open-source (SymbiFlow + yosys + nextpnr) and bitstreams load via DFU over USB. Prototypes and production boards exist: the FPGA boots, appears as DFU, and the RISC‑V core successfully counts theremin antenna frequencies, but the full audio path through the codec to speakers is still being completed.
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chapters (8)
- 0:00Start
- 3:47Carry Logic
- 19:47Recap
- 20:54Wishbone Bus
- 25:34Do You Have any Real World Problems for When You Use an Fpga versus a Traditional Mcu and Why
- 29:42What Would It Take To Expose the Fpga Wishbone Bus as an External Memory Device to the Esp Host Processor Eg Memory Mapped Gateway Peripherals
- 30:56Can We Have a Performance of the Theremin
- 31:30Diagnostic Tools
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