The state of Morello and CHERI
summary
CHERI is now portable across MIPS, RISC‑V and ARM-derived Morello platforms, with vendor efforts from Microsoft Chariot to a commercial CIP IP and about 600 Morello chips shipped to labs; a RISC‑V CHERI draft (CHERI‑5) is imminent. The software stack runs roughly 60–100 million lines of C compiled for capability pointers, and the team ships heap temporal safety for userland with pause times improved from ~30 ms to about 10 microsecond pause times. Research cores (tuba), Mel/Morello boards and Chariot microcontrollers all validate different tradeoffs in performance, compartmentalization and deployability.
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chapters (18)
- 0:00Introduction
- 1:03What is CHERI
- 3:50ISA refinements and trade-offs
- 7:03CHERI in real products
- 10:10Morello maturity
- 13:00RISC-V standardization
- 14:22Memory safety for C/C++
- 19:36FreeBSD temporal safety
- 23:45Heap safety and revocation
- 26:32Pointer analysis insights
- 27:56Undefined behavior
- 29:00CHERI vs Rust
- 30:23Procurement challenges
- 32:45Memory-safe browser
- 34:13Q&A: CHERI and Rust
- 34:57Q&A: formal verification
- 36:40Q&A: fragmentation
- 39:50Q&A: Rust and CHERI
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