When P4 Meets Run-to-completion Architecture
summary
P4RTC exposes P4 on a run‑to‑completion chip (Huawei 9800 FA1C prototype, 1.2 Tbps, 8 GB HBM) and adds concrete extensions: foreground pipeline and background pipeline, shared-memory tables, and control-flow ops like sleep/for_each. A compiler uses ILP to place, fragment and replicate tables across memory banks to avoid bottlenecks; a performance model (ESL simulator using code‑path probabilities) predicts latency/throughput under traffic shifts. A measurement system handles up to 50 million concurrent flows and emits <0.5% of input as aggregated flow records.
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chapters (11)
- 0:00P4 and run-to-completion intro
- 1:30Challenges in P4 networks
- 2:54Limitations of P4 switches
- 3:59Run-to-completion overview
- 5:04Challenges in P4TC development
- 6:06P4 language for run-to-completion
- 8:15P4TC compiler and tables
- 10:47Optimizing traffic patterns
- 11:30P4TC performance verification
- 12:31Case study: Flow measurement system
- 14:20Conclusion and benefits
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