Creating a Spider Goat: Security with Intel CPU Transactional Memory Support
summary
Shows how Intel TSX (Haswell/Xeon) uses XBEGIN/XEND to run a dedicated security thread that repeatedly reads protected RAM so any concurrent write triggers a hardware abort and can be attributed and optionally rolled back. Demo runs on a TSX-capable notebook and detects corruption of a simulated syscall table instantly. Protection works at 64-byte cache line granularity; practical limits include per-core transactional tracking (~32 KB), interrupts/context switches that abort transactions, and capacity-exhaustion DoS.
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chapters (8)
- 0:00Introduction and motivation
- 5:05Memory monitoring challenges
- 9:29Transactional memory explained
- 17:18Intel TSX mechanics
- 29:26Applying TSX for security
- 35:49Live demonstration
- 41:05Security applications and risks
- 48:28Evaluation and conclusion
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