Tiara: A Scalable and Efficient Hardware Acceleration Architecture for Stateful Layer-4
Talkat 19th USENIX Symposium on Networked Systems Design and Implementation (NSDI '22) · 2022-04-04..04-06·
summary
Tiara splits stateful L4 load balancing into memory-heavy real-server selection on FPGAs with HBM and throughput-heavy encapsulation on a programmable switch, plus x86 servers as a slow path. Prototype with 8 FPGAs hits 1.6 Tbps, offloads up to 80M concurrent flows, and sustains 1.8M new connections/s with <4 μs fast-path latency; details include an HBM-backed hash table (32M entries per FPGA), ECMP distribution, PCIe DMA offloading, and a lightweight aging and lock-free insertion pipeline.
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chapters (21)
- 0:00Intro
- 0:34L4 LB at datacenter boundary
- 1:01Being stateful
- 1:42Stateful L4 LB requirements
- 2:06Existing solution: software-based LB
- 3:01Existing solution: switch-based LB
- 3:50Strawman solution: switch-server LB
- 4:23Traffic at datacenter boundary
- 5:23System goals
- 5:48Tiara idea
- 7:15Tiara three-tier architecture
- 7:51Tiara architecture in details
- 8:57Inbound traffic: the first packet
- 10:14Inbound traffic: the rest packets
- 11:27Outbound traffic
- 11:45Optimizations
- 12:35Prototype implementation T-switch: Barefoot Tofino switch
- 13:44System performance
- 14:26Latency-bounded throughput
- 15:53Tiara vs. existing approaches
- 16:22Conclusion
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