Unlocking the Power of Inline Floating-Point Operations on Programmable Switches
Talkat 19th USENIX Symposium on Networked Systems Design and Implementation (NSDI '22) · 2022-04-04..04-06·
summary
Proposes FPISA, a compact floating-point representation and pipeline methods, implements it on Intel Tofino then identifies throughput and accuracy limits, and proposes hardware changes based on Banzai which are synthesized in a 15-nm standard-cell library to show feasibility. Uses emulation to build in-network accelerators for distributed ML training and query processing and shows FPISA uses 25–75% fewer CPU cores, yields up to 85.9% higher throughput than SwitchML in CPU-constrained settings, and enables up to 2.7× better throughput than Spark.
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chapters (10)
- 0:00Start
- 0:29Background & Motivation
- 2:13Challenges
- 7:27FPISA: High-level idea
- 8:00FPISA: FP representation and storage in
- 8:31FPISA: Delayed normalization
- 9:43FPISA: Leverage networking hardware
- 12:32Usecase: In-network aggregation for distributed ML
- 13:51Evaluation - Training accuracy and conv
- 14:23Evaluation - Training time speedup
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