Enabling In-situ Programmability in Network Data Plane: From Architecture to Language

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" summary

A new switch architecture and language extension enable changing protocol parsing, table layouts, and per-packet processing at runtime without stopping traffic: IPSA and rP4 compile incremental updates, use a template-based processor skeleton, a configurable interconnect and a disaggregated memory pool, and apply a big-bubble update to keep packets consistent. Implementations include the software switch ipbm and an FPGA prototype; FPGA costs are ~12.09% more LUTs and 9.69% more FFs, clocking 110.45 MHz, and pipeline downtime is only 0.34% of packets.

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" chapters (14)

1. 0:00Intro
2. 0:29Development of Switching ASIC
3. 0:58Motivations
4. 2:18Programmability in PISA - Protocol (why not)
5. 2:52Programmability in PISA - Processing Logic w
6. 3:30Programmability in PISA - Memory
7. 3:55IPSA vs. PISA (how we solve limitations of PISA)
8. 5:01IPSA - Template-based Stage Processor why can
9. 8:02IPSA - Big Bubble Update
10. 9:22Workflow of rP4 (r - reconfigurable)
11. 10:32Use Case
12. 11:36Evaluation - Resources
13. 12:53Evaluation - Update Performance
14. 13:33Conclusion

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