Enabling Lightweight, High-Performance FSDP With NVIDIA GPU
summary
Megatron‑FSDP is a PyTorch‑compatible FSDP implementation that reaches ~2020 TFLOPS (versus 1340 TFLOPS baseline) on Llama 3 4.5B across 64 B200/GB200 GPUs by combining persistent communication buffers, NVLink/InfiniBand‑SHARP offload and TransformerEngine FP8 support. It removes a ~10% permutation copy by writing gradients directly to reduction buffers, uses zero‑copy NIC registration to cut SM usage (5–8% gain), offloads 76% of activations to CPU on Grace to reclaim memory and claims ~25% speedup from activation offload.
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chapters (17)
- 0:00Megatron FSDP intro
- 1:04Fully Sharded Data Parallelism
- 3:11FSDP performance needs
- 4:35Three optimization categories
- 5:59Sharding in Megatron FSDP
- 7:25Collective buffer overhead
- 9:10Communication performance issues
- 10:35NVIDIA MB Link optimizations
- 12:24Gradient copy overhead
- 13:50Hiding comms with offload
- 15:59Memory efficiency in hybrid FSDP
- 19:52Performance results summary
- 20:13Megatron FSDP API
- 23:03Device mesh integration
- 23:46Checkpointing compatibility
- 24:51Installation and support
- 25:34Q&A
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