Keynote: Enabling PyTorch’s Thousand Ops for Software First Silicon Design
summary
Claims a hardware first redesign that makes compilation simple by making the architecture deterministic and software controlled and shows it works on inference workloads. Builds an LPU of linear 1D SIMD lanes with 320 byte vectors and four unit types (MXM, SXM, MEM, VEC), exposes flat physical-addressed memory, 1D SIMD lanes with 320‑byte vectors, has the compiler assign every physical address, and canonicalizes thousands of PyTorch ops → tens of operators to get practical token throughput.
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chapters (8)
- 0:00Grock and compute scarcity
- 1:47PyTorch as ML lingua franca
- 3:12PyTorch ops explosion challenges
- 4:58Compiler challenges parallel algorithms
- 7:07Grock’s deterministic architecture
- 8:32Canonicalizing thousands of ops
- 9:55Grock LPU functional units
- 10:58PyTorch shaping hardware design
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