Recap: Unveiling Insights - A Two Day Conference Retrospective
summary
Conference recap reports concrete artifacts and limits: a PQC IP core runs on average FPGAs in 300–600 µs at security level 5 and promises ~10× speedup in silicon, current HSMs/Chip vendors demonstrate deployable PQ primitives with firmware updates though throughput and RAM tradeoffs increase load, smart cards may need selective algorithm choices, side‑channel hardening remains unsolved for many code‑based and FO transforms, and live testbeds like Cloudflare and SIDN Labs testbeds show practical interoperability and reveal integration bugs.
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chapters (14)
- 0:00Conference overview
- 1:53IBM and NXP takeaways
- 3:59Financial incentives for first movers
- 5:47Threat focus shift to decrypt later
- 7:16Regulation and risk timelines
- 9:05Postquantum cryptography standards
- 11:55Government collaboration networks
- 15:09Hardware challenges in embedded systems
- 17:39Business adoption and risk communication
- 20:07Postquantum cryptographic evolution
- 21:51Immediate actions for organizations
- 24:59Critical infrastructure dilemma
- 26:03Testing and implementation collaboration
- 27:27Closing remarks
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