All you need is Superword-Level Parallelism: Systematic Control-Flow Vectorization with SLP
summary
This work generalizes SLP vectorization to pack independent, isomorphic instructions across different control-flow regions by converting code to predicated SSA that tracks predicates per instruction, adding active flags and mu nodes to preserve loop-liveness, fusing loops, rewriting predicates, and emitting masked vector ops. Implementation vectorizes 6 of 7 hard LLVM benchmarks (vs LLVM's loop+SLP) and reports on-average >80% speedup; it matches ISPC on some cases like the volume renderer.
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chapters (11)
- 0:00Intro
- 0:16Background: Loop Vectorization
- 0:38Background: SLP Vectorization
- 1:27Motivation: Exploiting ILP among different loops
- 3:33Idea: an IR that makes code motion trivial
- 4:55Predicated SSA
- 7:20Scheduling: Rewriting Predicates
- 8:37Scheduling: Guard Live-Out Values
- 10:38Vector Code Generation
- 12:00Vectorizing ISPC's serial baseline
- 13:32Conclusion and Future Work
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