Accelerating the Next Gen Datacenter with DPUs Continued
summary
Fungible presents a DPU-based stack: a chip and OS that offloads data paths to enable a composable datacenter. The storage cluster uses two DPUs per chassis (each with 600 Gbps ports and controlling 12 NVMe drives) and delivers up to 13 million IOPS from a single node; with a host-side DPU hardware initiator tests hit 10 million IOPS while cutting host CPU use by about 75%. Erasure coding hardware accelerators shrink replication overhead (4+2 → 50%, 8+2 → 25%, 14+2 → 14%). GPU Connect (fx108 + fc200) shows ~1–2% performance loss vs. local PCIe and initially qualifies NVIDIA A2–A100; MIG and multi-vendor support are under validation.
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chapters (26)
- 0:00Intro
- 1:19Data is growing
- 1:41Moores Law
- 2:52Data Processing Unit
- 3:43History of DPUs
- 4:49Datacentric computations
- 6:12Datacentric workload definition
- 7:05DPUs as endpoints
- 8:18What is Fungible
- 9:40Fungible Storage Cluster
- 9:56Scale Out Block Storage
- 11:18Hardware Overview
- 12:35erasure coding
- 14:17community involvement
- 14:54hardware storage initiator
- 16:37test results
- 18:20fungible gpu connect
- 18:30why consolidate gpus
- 19:52fungible solution
- 20:45example
- 21:54user interface
- 22:29GPU view
- 23:06Performance
- 23:38Benchmarks
- 24:38Wrap Up
- 25:30QA