AlNiCo: SmartNIC-accelerated Contention-aware Request Scheduling for Transaction...

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" summary

AlNiCo uses FPGA-equipped Innova-2 SmartNICs to perform low-overhead, contention-aware scheduling of incoming transaction requests to CPU cores. It encodes system contention state into a SmartNIC-friendly representation and co-designs hardware and software to adapt scheduling decisions at line rate, aiming to reduce inter-transaction contention and improve throughput and latency.

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" chapters (14)

1. 0:00Start
2. 0:38Transaction Request Scheduling
3. 1:18Existing Scheduling Methods
4. 3:32Challenges
5. 4:26Overview
6. 5:30Key Designs
7. 6:09States for Scheduling: Vectors (1)
8. 10:54Software Feedback Mechanism
9. 12:54Implementation on Mellanox Innova-2
10. 14:23Outline
11. 15:47Overall Performance (Throughput)
12. 16:52Overall Performance (Latency)
13. 17:27Generality
14. 19:49Summary

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