AlNiCo: SmartNIC-accelerated Contention-aware Request Scheduling for Transaction...
summary
AlNiCo uses FPGA-equipped Innova-2 SmartNICs to perform low-overhead, contention-aware scheduling of incoming transaction requests to CPU cores. It encodes system contention state into a SmartNIC-friendly representation and co-designs hardware and software to adapt scheduling decisions at line rate, aiming to reduce inter-transaction contention and improve throughput and latency.
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chapters (14)
- 0:00Start
- 0:38Transaction Request Scheduling
- 1:18Existing Scheduling Methods
- 3:32Challenges
- 4:26Overview
- 5:30Key Designs
- 6:09States for Scheduling: Vectors (1)
- 10:54Software Feedback Mechanism
- 12:54Implementation on Mellanox Innova-2
- 14:23Outline
- 15:47Overall Performance (Throughput)
- 16:52Overall Performance (Latency)
- 17:27Generality
- 19:49Summary
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