Floating point computations today and in the future
summary
Explains concrete tradeoffs: IEEE 754 causes nonassociative rounding and subnormal slowdowns; 16‑bit floats (FP16, standardized 2008) often suffice for neural nets; tensor compressors like ZFP and SZ and an FP‑specific library yield large savings (example run shows high compression with mean squared error ~0.63 on random data); a C++ implementation cpposit demonstrates POSIT arithmetic (variable regime bits, a 12‑bit posit example) usable today in software though no mainstream CPU hardware exists; reinforcement learning (AlphaTensor) even finds faster 4×4 matrix multiplication.
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chapters (9)
- 0:00Introduction
- 2:50Data transfer bottlenecks
- 5:01IEEE 754 limitations
- 10:2216-bit floats matter
- 27:16ZFP for float compression
- 39:47Posit arithmetic future
- 53:20Faster matrix multiplication
- 59:49Posit hardware support
- 1:03:20Q&A
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