Trading at light speed: designing low latency systems in C++
summary
Claims concrete wins: designing for cache locality drops working set from ~400 MB (node‑based map) to ~1 MB (custom stable vector), targets software latencies around 2.5 μs and exchange trigger→target pockets near 10 μs, and achieves ~60M msgs/s with one reader and ~20M msgs/s with 10 readers using a custom SPMC queue v2. Tools and checks include rdtsc timing, WSS measurements, in‑house clang xray profiling and system tuning (disable C‑states/P‑states, huge pages). Code and benchmarks are built and measured, not just promised.
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chapters (21)
- 0:00Introduction
- 0:11AUTOMATED TRADING A HIGH STAKES GAME
- 1:40AUTOMATED TRADING: THE NEED FOR SPEED
- 4:34DESIGN FOR PERFORMANCE
- 5:48STRATEGY & TACTICS
- 7:42HOW FAST IS FAST?
- 15:24AN UNDERWHELMING PROFILING RESULT
- 16:34DATA MODEL FOR PERFORMANCE
- 19:06DATA MODEL: INSTRUMENT STORE
- 22:23STABLE VECTOR
- 24:46WSS ESTIMATION
- 27:55CONCURRENT DATA IN TRADING SYSTEMS
- 29:21HOW MUCH DATA?
- 35:06SEQLOCK PROPERTIES
- 37:33CONCURRENT DATA: EVENTS
- 38:37SPMC QUEUE V2
- 47:00IS YOUR SYSTEM TUNED CORRECTLY?
- 48:28C-STATE, P-STATE
- 50:36SHARED LLC OPTIMIZATION
- 53:53METRICS
- 57:59CONCLUSION
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