Foundation of GPU Programming
summary
Claims that GPU throughput comes from massive SIMD lanes plus memory design and shows concrete hardware and software artifacts: A100/H100 block diagrams, HBM stacking via TSVs, and a working vector-add CUDA kernel with launch configuration and block/thread indexing. Explains bank‑level parallelism, warp = 32 lanes grouping, occupancy targets, bank‑conflict examples, shared‑memory as a programmer‑managed scratchpad, and simulator tools from the SAFARI research group including an "app mem" processing‑in‑memory chip; demonstrates which changes actually raise measured throughput versus just changing the topic.
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chapters (13)
- 0:00GPU programming foundations
- 4:05Motivation for using GPUs over CPUs
- 5:49Data parallelism basics
- 18:30GPU architecture blend
- 22:24Programming vs execution models
- 29:48SIMT execution model
- 36:50Fine-grained threading
- 41:42GPU programming challenges
- 45:16CPU-GPU data transfer
- 50:14CUDA vector addition
- 57:17GPU memory hierarchy
- 1:00:27Optimization strategies
- 1:05:05Q&A
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