NicPic: Scalable and Accurate End-Host Rate Limiting
summary
Proposes NicPic: move per-class queues into host DRAM and keep only small metadata/SRAM and a tiny FIFO on the NIC, so the CPU enqueues and configures thousands of classes in host memory while the NIC does real-time scheduling and DMA-pulls packets on demand. Back-of-envelope: 20 VMs × 50 peers → ~2,500 rate limiters, so scalability targets are thousands. Evaluation (extrapolating an Intel NIC): at 5 Gbps software HTB uses ~4–5× more CPU and shows larger bursts; at 9 Gbps software cannot reach line rate while the hardware approach can.
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chapters (15)
- 0:00Intro
- 0:25Consolidation of Servers
- 0:56Infrastructure Commoditization (Compute, Networking, and Storage)
- 2:06Resource Management
- 2:57Programmable Rate Limiters
- 4:08Bandwidth Allocation Example
- 6:01How many rate limiters are needed?
- 6:50Rate Limiter Options
- 9:35Current NIC Design
- 10:55NIC and CPU/OS strengths
- 12:06Key Idea 1: Use host RAM for storing per-traffic-class queues
- 14:39Proposed NIC Design
- 15:35Expected Performance
- 18:44Implications
- 19:56NicPic
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