Achieving 10Gbps Line-rate Key-value Stores with FPGAs
summary
An FPGA-based memcached appliance is implemented on a NIC using a dataflow pipeline that parses, hashes, looks up a 2M-entry table and fetches values from DRAM on-board, delivering 10Gbps line-rate for all packet sizes and sustaining up to 13M req/s while consuming ~50W for the FPGA subsystem (120W host total), yielding roughly 36x higher requests/sec/W and 3.4–4.5 µs latency. Prototype supports ASCII/binary, get/set/delete/flush; limits include 64 TCP sessions, reduced protocol coverage and high development NRE.
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chapters (13)
- 0:00Introduction
- 2:19Typical Memcached Implementations
- 3:54What are FPGAs?
- 5:14Programming FPGAs?
- 6:50Why Dataflow Architectures?
- 7:48System-level Architecture
- 9:13FPGA-based Dataflow Architecture
- 13:47Hash Table architecture
- 15:08System Test Setup
- 16:34Power - Test Setup & Results
- 16:58Results - Performance
- 18:21First Results of Memcached Evaluation
- 20:43Current Platform Limitations
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