Integrated Host-SSD Mapping Table Management for Improving User Experience of Smartphones
summary
Prototype HPBvalve integrates foreground app-centric caching with dynamic HPB resizing to reduce L2P miss penalties on a Snapdragon 888 dev board (12 GB DRAM, 1 TB flash, 1 GB mapping table). The kernel/driver implementation prefetches profiled L2P entries for launched apps and aggressively reclaims HPB on memory pressure, yielding average app launch time improvement of 23% and up to 43% (250 ms), L2P mapping misses cut by up to 78%, 25% fewer total app kills and ~70% fewer high‑priority app kills.
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chapters (8)
- 0:00Introduction to HPB latency
- 1:34HPB challenges and overheads
- 4:01Shortcomings of current HPB
- 7:13Proposed HPB Valve design
- 9:14Root causes of performance
- 13:37HPB Valve implementation
- 16:37Experimental evaluation
- 19:15Conclusion and future work
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