ACCL+: an FPGA-Based Collective Engine for Distributed Applications
Talkat 18th USENIX Symposium on Operating Systems Design and Implementation (OSDI '24) · 2024-07-10..07-12·
summary
ACCL+ is an open-source FPGA collective library that enables direct FPGA-to-FPGA collectives over UDP TCP and RDMA, claims firmware-updatable collective implementations without resynthesis, and exposes a streaming API for overlap of compute and communication. It pairs a microcontroller-based control plane with a 512-bit hardware data plane, saturates 100 Gb/s links, beats software MPI over RDMA on 8-node latency, and shows >10x throughput and ~100x lower latency for a distributed recommendation inference use case. collective offload engine streaming channels
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chapters (9)
- 0:00ACCL+ introduction
- 2:32ACCL+ design goals
- 4:35Collective Offload Engine
- 8:03ACCL+ use cases
- 9:51ACCL+ as smart NIC
- 10:13ACCL+ performance
- 11:41Latency and flexibility
- 12:24Deep learning demo
- 14:35Conclusion and open-source
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