Non-Newtonian Hardware Design for Longevity
summary
Proposes a modular accelerator methodology called Cohort and shows a hardware prototype: a three-stage multiplier implemented as chained micro-accelerators using software-assured memory queues instead of MMIO/DMA. Measures show a roughly 5x improvement over naive per-call software fallbacks and further gains when staying in hardware; when the middle stage fails it falls back to software only for that stage, preserving most throughput. Also evaluates using a hot-spare FPGA for near-ASIC recovery and argues for semantically equivalent functional descriptions (mentions Shake flow and Rust-like pseudocode) to auto-derive software fallbacks.
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