New Embedded DSLs for Hardware Design and Verification
summary
Argues for mixed-abstraction HDLs and presents three Scala eDSLs specialized for testbench description, stimulus generation, and control-flow compilation, claiming they make composition of RTL, dataflow, lightweight HLS and event-driven fragments practical. Recommends latency‑insensitive interfaces or Verilog-style scheduling for cross‑abstraction boundaries, preserving high‑level semantics through IR lowering (not black‑boxing PDK SRAMs), and incremental elaboration via term-level hashing / content‑addressable caching to avoid full re‑elaboration on small changes.
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