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Jonathan Balkind

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Fungible Memories for Automated Technology Mapping and RetargetingPLDI 20262026-06-15
Memo implements a write-once, map-anywhere memory abstraction that automatically retargets memories across simulation, FPGA and ASIC backends, and lifts…
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Improving Equality Saturation for EDA via Semantic E-GraphsPLDI 20262026-06-15
Introduces semantic e-graphs as an e-graph variant that encodes semantic IDs to link word- and bit-level hardware representations, and implements Nextmap, an…
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OpeningLatch-Up 20252025-05-02
About 100 attendees register for a two‑day program Friday–Saturday with an unconference Sunday, talks timed at 15–25 minutes and lightning sessions at the…
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Semi-Automated Translation of a Formal ISA Specification to HardwarePLARCH 20232023-06-17
Prototype pipeline converts Sail ISA specs into Clash hardware by translating Sail’s monadic effects into monadic stream functions that compile to a naive…
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Loop Rerolling for Hardware DecompilationPLDI 20232023-06-17
Defines hardware loop rerolling to recover syntactic loops from netlists by combining clone detection with sketch-based program synthesis using Rosette, and…
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Non-Newtonian Hardware Design for LongevityPLARCH 20232023-06-17
Proposes a modular accelerator methodology called Cohort and shows a hardware prototype: a three-stage multiplier implemented as chained micro-accelerators…
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On the Generality of Matrix MultiplicationPLARCH 20232023-06-17
Claims a concrete mapping from a Turing-complete one-instruction-set ISA into sequences of matrix multiplications and uses a Rosette-based synthesizer to…
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Building Cache Coherent, Heterogeneous-ISA Processors Using P-MeshOpenPOWER Summit NA 20202020-09-15
P-Mesh gets reworked to be ISA-agnostic by adding a simple Transaction-Response Interface and L2/LLC support for ISA-specific atomics, connecting more than 10…
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