Integrated Circuit Offensive Security
summary
Shows a practical IC offensive flow: chemical and CMP thinning, SEM imaging producing ~200 GB per project, automated feature extraction into a VHDL netlist, and simulation to validate attacks. Demonstrates tools (ARES-style automation), traces a register chain to reveal a scan/JTAG path, locates ~1,000,000 contacts and 28,000 standard cells on one die, and exports a working HDL in minutes to simulate ROM de-scrambling and perform linear code-extraction and targeted fault-injection (laser/EM) attacks.
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chapters (9)
- 0:00Intro
- 1:08About Texplained
- 2:51Reverse Engineering
- 5:29G Processing
- 14:11Digital Logic
- 20:02Netlists
- 26:32Simulation
- 33:07Common Criteria
- 35:12Risk Assessments
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