The foundation of embedded DRAM Memory
summary
Explains eDRAM structure down to mats, rows, bitlines and sense amplifiers and gives concrete timings (DRAM refresh interval 64 ms, typical activate→read delays on the order of tens of ns) and system numbers — capacity grows ~128×, bandwidth ~20×, latency barely changes — to show why latency and refresh dominate. Covers measured refresh energy and runtime impacts on multi-GB chips, use of eDRAM as on-die buffers for accelerators, and concrete mitigation: per-bank refresh, violating timing parameters to trade errors for power/speed and training models with those error models.
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chapters (10)
- 0:00Introduction and background
- 6:11DRAM microarchitecture basics
- 11:40DRAM read/write life cycle
- 16:16Memory controller challenges
- 19:03Memory bottlenecks in systems
- 22:20Why DRAM latencies are long
- 24:08DRAM refresh overhead
- 25:54Violating timing parameters
- 29:49Training resilient workloads
- 31:21Q&A session
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