Unlocking the Potential of Suspend to RAM Using Linux in a Multi-Core, Multi-Fi...
summary
Suspend-to-RAM is implemented on a TI DRA821 Jacinto K3 SoC with A72, R5 and M3 cores using TF-A, U-Boot, OP-TEE and a custom DM firmware; DDR goes to self-refresh, the R5 copies a tiny resume stub into SRAM and writes a PIC scratch register magic so the PIC can cold-power off the chip and later wake it. TF-A normally lives in SRAM so the resume flow reloads a signed TF-A image, restores saved context and resumes userland, achieving resume <2s versus cold boots of ~10–30s; workarounds for TF-A in SRAM loss, L3 cache flushes and a new SPL/TFS decrypt + firewall handoff address remaining security gaps.
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chapters (15)
- 0:00Suspend to RAM in automotive
- 5:03DRA821 SoC hardware
- 15:16Implementing suspend to RAM
- 20:48Linux driver changes
- 22:58TF-A firmware context
- 26:17DM firmware role
- 29:58U-Boot SPL resume
- 32:13Cache sync challenges
- 34:25Security in suspend to RAM
- 39:28Custom firmware handling
- 41:59Porting to K3 SoCs
- 42:46Power modes comparison
- 45:39Suspend to idle vs RAM
- 47:05Boot time with suspend
- 48:11Q&A
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