Enemy of the State, Understanding the Many Flavors of Race Conditions
summary
Explains concrete race sources beyond threads: interrupt handlers and signals run on another thread’s stack and must win resource contention, so lock-free patterns replace mutexes. Shows ARM load-exclusive/store-exclusive (LDREX/STREX) used to build a correct multi-producer singly linked queue where stores return success/fail and the loser retries — inexpensive on microcontrollers due to a single-core shortcut. Demonstrates surprising hardware latency: disabling a timer can still trigger an interrupt because the peripheral sits on APB1 up to 42 MHz, so a data synchronization barrier (DSB) is required.
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chapters (7)
- 0:00Introduction
- 1:05Compiler World
- 3:10Interrupt Service
- 4:00Sharing Stacks
- 5:10Sharing Signals
- 7:05Linked Load semantics
- 8:55Multiple interrupt priorities
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