Unlocking the Potential of Suspend to RAM Using Linux in a Multi-Core, Multi-Fi...
summary
Implements Suspend-to-RAM on a TI DRA821 Jacinto SoC with heterogeneous cores (A72, R5, M3) using TF-A + U-Boot flow, DM firmware and PIC-managed DDR self‑refresh; suspension saves TFA context to DDR/PIC scratch, powers the SoC off, and on wake the bootloader detects a resume flag and restores state. Addresses L3 cache flushing, firewall/signature constraints by reloading signed images and planning TFS-assisted encryption, keeps copies in DDR to avoid storage reads, and achieves resume <2s in practice.
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chapters (15)
- 0:00Suspend to RAM in automotive
- 5:03DRA821 SoC hardware
- 15:16Implementing suspend to RAM
- 20:48Linux driver changes
- 22:58TF-A firmware context
- 26:17DM firmware role
- 29:58U-Boot SPL resume
- 32:13Cache sync challenges
- 34:25Security in suspend to RAM
- 39:28Custom firmware handling
- 41:59Porting to K3 SoCs
- 42:46Power modes comparison
- 45:39Suspend to idle vs RAM
- 47:05Boot time with suspend
- 48:11Q&A
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