Are Polar Codes Practical?
summary
Successive cancellation decoding is serial and looks like N log N work but schedules down to about N and then to a small constant number of PEs, so hardware is practical. A 1,024‑bit, rate‑1/2 ASIC hits about 50 Mbps ASIC (mostly memory), an FPGA semi‑parallel design reaches ~1 Gbps FPGA for 32K codes, and an unrolled pipelined design reaches ~118 Gbps pipeline (237 Gbps coded). CRC‑aided list decoding (L=64) matches LDPC FER; a Fast‑SSC then list fallback keeps throughput high while improving finite‑length performance.
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chapters (21)
- 0:00Intro
- 0:41Achieving the Channel Capacity
- 1:39Channel Polarization
- 3:35Successive Cancellation Decoding
- 6:08Semi-Parallel SC Decoder Implementation
- 9:02FPGA Implementation
- 10:34Throughput of SC Decoders
- 11:23Successive Cancellation Tree
- 13:34Simplified Successive-Cancellation Decoding
- 15:37Fast-SSC Decoding-New Nodes
- 16:05SSC and Fast-SSC Trees—256, 230
- 17:46Fast-SSC Decoder Implementation
- 18:27Throughput of Hardware Decoders
- 19:54The Unrolled Decoder Implementation
- 21:09SDR and Modern Software ECC
- 22:40Fixed-Point Software Polar Decoders
- 23:31Improving Finite-Length Error-Correction Performance
- 23:48List Decoding
- 24:23ASIC Implementation
- 24:46Two-Step SW List Decoder
- 26:51Conclusion
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