New Problems in Coding Theory with Applications to Modern Data Storage and Memories

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Measurements on a TLC device (TLC (3 bits/cell)) show raw wear-out can kill lifetime in months and errors concentrate as one bit per symbol. A construction using tensor-product graded-bit codes with parameters T1,T2,L1,L2 targets the observed symbol-and-bit patterns and moves the reliability curves right on real-device tests. A q-ary VOM extension of Rivest–Shamir yields sum-rate 4.5 vs capacity 5.17. Optimized non-binary LDPC codes beat BCH on frame-error plots.

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" chapters (17)

1. 0:00Intro
2. 1:44Operating constraints and challenges for NVMs
3. 7:02Simultaneously controlling the number of erroneous cells and the number of erroneous bits
4. 9:22New code constructions target more realistic errors
5. 12:24Variability-aware coding for flash improves lifetime
6. 15:04WOM-codes for multi-level flash memories
7. 16:34The original WOM code
8. 18:13WOM codes: properties and characterization
9. 19:46A construction of non-binary WOM codes
10. 23:00An example using Rivest and Shamir write-twice code for
11. 23:43Constructing high-rate non-binary WOM codes
12. 26:30Inter-Cell Coupling in Rank Modulation: Example
13. 28:04Bounds on Code Cardinalities
14. 28:25Capacity results
15. 28:52Dynamic Thresholds for Flash Memories
16. 29:48Research problems on coding for spatio-temporal variability in NVMs
17. 31:04Research problems beyond coding