Automated design space exploration and generation of AI accelerators
Talkat Algorithmic Foundations for Emerging Computing Technologies Boot Camp 2025 · 2025-09-08..09-12·
summary
A high-level HLS-based generator converts parameterized C++ templates into synthesis-ready Verilog, runs PyTorch->TorchDynamo graphs through quantization, fusion, tiling and a compiler, and produces taped-out chips; it explores datatype, scaling granularity, compute parallelism and memory sizes and reports concrete results: a 32x32 systolic array reaches 98% MAC utilization, 64x64 shows underutilization, comparisons beat Gemini/Simba in latency (43 ms → 17 ms) and match or improve hand-tuned RTL while enabling automated design-space search.
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chapters (11)
- 0:00Introduction and motivation
- 1:32Challenges in AI acceleration
- 7:02Defining the design space
- 9:32High-level synthesis benefits
- 17:25HLS adoption hurdles
- 19:17The Voyager template system
- 25:03Compiler and generation flow
- 31:43Evaluation and results
- 43:55Benchmarking non-traditional tech
- 52:43Sparsity vs. quantization study
- 59:18Conclusion and Q&A
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