TensorPRAM: Designing a Scalable Heterogeneous Deep Learning Accelerator
Talkat 12th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage '20) · 2020-07-13..07-14·
summary
Design replaces DRAM with byte-addressable PRAM inside an FPGA-based accelerator so model weights and activations sit on nonvolatile memory and avoid host-device copies. Evaluation uses MLP workloads and compares CPUx, DNNx (DRAM + accel), and TensorPRAM. Results show 1,350× execution speedup over CPUx, DNNx spends ~60% of cycles on data movement while TensorPRAM cuts that substantially, and energy drops 61% vs DNNx with an FPGA implementation that demonstrates the claimed gains.
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chapters (7)
- 0:00Introduction
- 0:44Challenge: Data movement overhe
- 1:39Solution: Reduction of data movementov
- 2:46Evaluation: Execution Cycle Compari
- 3:19Evaluation: Execution Cycle Breakdo
- 4:05Evaluation: Energy Consumption
- 4:39Conclusion
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