Automated, Simulation-Based Flow for Low-Cost FPGA-Accelerated Devices with Zeph...
summary
PolarFire SoC with 4+1 RISC‑V cores and an integrated FPGA is now usable on BeagleV‑Fire at ~$150 with a contributed Zephyr port, a Renode model and VS Code / VSD integration. The demo generates device trees from a visual graph, compiles Zephyr, and runs the same binary in Renode while Renode co‑simulation from Verilog drives a memory‑mapped FPGA peripheral; UART and shell work (slower in RTL sim). FPGA bitstream still requires vendor tooling and separate programming.
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chapters (15)
- 0:00Automated simulation flow
- 1:47About Antmicro and RISC-V Zephyr
- 3:15Renode simulation framework
- 5:23PolarFire SoC overview
- 7:12BeagleV Fire affordability
- 9:19FPGA acceleration use cases
- 11:56Microchip’s Zephyr contributions
- 13:24Zephyr modularity advantages
- 15:57Zephyr Dashboard CI
- 18:30Visual System Designer
- 21:46FPGA payload integration challenges
- 23:58Demo: Custom platform creation
- 33:42Demo summary open-source benefits
- 35:49Future plans community
- 37:58Q&A FPGA Linux
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