Keynote: First Generation of Meta’s Datacenter Accelerators
summary
Meta unveils two first‑gen datacenter chips: MTIA (inference‑focused) and MSVP (video transcoding). MTIA uses an 8×8 PE mesh of customized RISC‑V cores with vector extensions, LPDDR5 up to 128 GB, SRAM, and system firmware running Zephyr RTOS LTS. Pre‑silicon development leans on emulation and a complex test harness; published benchmarks show good perf/watt on low‑to‑medium recommendation models but lag GPUs on high‑complexity workloads. Build and CI integrate with Buck (Buck2) in Rust and remote execution.
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chapters (7)
- 0:00Start
- 0:24What do we do?
- 9:24Device Firmware Development
- 10:33Developing for Emulation
- 11:20Continuous Testing
- 12:33Zephyr integration with Meta's infrastructure
- 14:30Conclusion
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