~/talk

Overcoming the Memory Wall with CXL-Enabled SSD

Talkat USENIX ATC '23 · 2023-07-10..07-12
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name:Eunji Lee
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Study builds a physical memory tracer and a trace-driven simulator to model CXL-enabled SSDs and integrates a DRAM cache, MSHR and several prefetchers to address granularity mismatch, repeated flash reads and high latency. Evaluation on real-world traces reports 68–91% of requests served within one microsecond and an estimated device lifetime of at least 3.1 years for the worst-case workload. Results show prefetch accuracy and cache pollution drive wins or losses and virtual-to-physical translation needs kernel hints to help the device.

AI-written summary · about

  1. 0:00Introduction
  2. 0:33Memory wall and CXL context
  3. 2:42Challenges and design tools
  4. 4:41Memory tracing methodology
  5. 6:42Design of CXL flash system
  6. 10:28Evaluation and results
  7. 16:14Future work and conclusion
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