Towards Understanding the Costs of Avoiding Out-of-Thin-Air Results
summary
Paper implements two concrete fixes in LLVM and measures cost on ARMv8 Cortex‑A72 hardware. One enforces load/store ordering for atomics by adding fences or bogus branches and runs 43 concurrent C++ data‑structure workloads with no average overhead and up to 6.3% worst case. The other enforces dependency‑preserving semantics by auditing IR and backend passes, evaluates on SPEC CPU2006, and shows ~3.1% average slowdown and up to 17.6% peak.
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chapters (5)
- 0:00Start
- 3:53Causality Cycle
- 8:22Preserve Dependencies at the Ir Level
- 11:36Partial Optimization
- 14:37Preserve Load Store Ordering for Atomic Operations
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