Benchmarking The Static Power Vulnerability Of Four CMOS Generations
summary
Custom ICs in 90nm, 65nm, 40nm, 28nm chips host identical AES-128 cores and undergo controlled static-power side‑channel measurements using a climate chamber, low‑noise DC amplification and a source meter. Results show vulnerability rises as feature size shrinks: each generation reduces required traces by roughly an order of magnitude under nominal conditions, and voltage/temperature boosts make attacks easier. Practical countermeasure tests show 600k traces to break masked+shuffle and up to ~3M traces for the strongest variant, so some mitigations help but do not eliminate the leakage.
AI-written summary · about
chapters (9)
- 0:00Introduction and context
- 1:40Static power side channels
- 3:42Impact of technology scaling
- 8:42Hardware prototyping
- 12:44Measurement methodology
- 17:31Empirical results
- 20:17Security analysis
- 25:05Countermeasures and masking
- 30:45Conclusion and Q&A
related talks
01h 01mSecurity: from Transistors to Compilers
36mCollide+Power: The Evolution of Software-based Power Side-Channels Attacks
01h 02mCryptographic Side-Channels on Embedded Devices
44mSilicon Under Attack Physical Exploitation Of Modern Chips
45mIntegrated Circuit Offensive Security
42mEscaping The Sandbox: Side Channel Shenanigans On Our DIY Chip
01h 01mTutorial: Side-Channel Attacks and Transient Execution Vulnerab...
44mState-of-the-Art Anti-Counterfeiting: Attacks And Countermeasures