Sigrok: Using Logic to Debug Logic
summary
Sigrok provides a device-agnostic capture format and tools that glue cheap logic analyzers, DSOs and JTAG into a single workflow it ships Python protocol decoders and a GUI PulseView while backends and firmware (Cypress FX2 hacks for Saleae clones) let low-end hardware work for most I2C SPI UART tasks. Known limits include the Open Logic Sniffer’s 24k sample buffer and noisy probes despite advertised 100–200 MHz, USB timeouts on Saleae Logic 16, and missing serial and multistage hardware triggers.
AI-written summary · about
chapters (9)
- 0:00Start
- 1:23Meet The Family
- 2:59sigrok Components
- 4:25Supported Devices
- 6:02sigrok Metadata
- 6:21sigrok Probe Data
- 12:03Creating Protocol Decoders
- 20:08Demo
- 27:15Questions?
related talks
27mLook inside your SoC with Open SoC Debug
32mSecSi Product Development
21mScanalog: Interactive Design and Debugging of Analog Circuits with Programmable Hardware
20mOpen-Source FPGAs: Tools, Flows, and Visualization
37mIt's a Hardware Bug and I can Prove It
11mDriving SoC Innovation with Synopsys RISC-V Solutions
16mEfficient debug and trace of RISC-V systems: a hardware/software co-design approach
20mBifröst : Visualizing and Checking Behavior of Embedded Systems across Hardware and Software
