World’s 1st racing-the-beam ray tracer on discarded FPGA hardware!!!
summary
A scanline ray tracer runs on discarded Pano Logic G1 hardware bought in bulk on eBay, using a racing the beam approach so no frame buffer or DRAM is required. The pipeline implements ~115 floating‑point ops and is ~85 clocks deep, uses limited‑precision floating point, and targets ~6 fps at 640×480. Hardware synthesis uses SpinalHDL and pushes the FPGA to the limit — roughly 99% of slices and 32 of 36 multipliers — and the demo actually works.
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chapters (10)
- 0:00Discarded FPGA hardware
- 1:04Reverse engineering Pano Logic G1
- 2:54Retro demos and racing the beam
- 4:28Ray tracing fits racing-the-beam
- 5:31Reducing ray tracing complexity
- 6:34Pixel operations and hardware pipeline
- 8:07Ray tracing pipeline in SpinalHDL
- 9:21Debugging FPGA implementation
- 10:28FPGA resource usage
- 10:52Live ray tracer demo
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