Beyond Sequential Consistency - Leveraging Atomics for Fun & Profit
summary
C++ atomics are measured end-to-end on a lock‑free ring buffer: default sequentially consistent code hits about 10M ops/s on an Intel Xeon, switching to explicit acquire/release removes the locked fetch_add and jumps to 170M ops/s, adding cacheline alignment raises it to ~220M, and a cached‑index trick yields nearly a 3x further speedup (hundreds of millions ops/s). x86’s strong coherence makes acquire/release effectively free, while ARM requires explicit fences, observed via Compiler Explorer disassembly and benchmarks (slides on GitHub).
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chapters (29)
- 0:00Introduction
- 0:31Talk overview
- 1:35Concepts and data structure
- 2:35Disclaimers and correctness
- 4:42What is lock-free programming
- 5:55Atomic operations example
- 9:16C++ memory model overview
- 10:42SMP machine architecture
- 12:46Memory fences and barriers
- 15:52Sequential consistency
- 19:14Acquire release semantics
- 23:17Relaxed memory ordering
- 27:28Lock free ring buffer design
- 30:42Prototypical queue implementation
- 35:28Naive queue performance
- 38:12Optimizing memory ordering
- 40:35False sharing and alignment
- 42:30Performance benchmarking results
- 45:12Large data size performance
- 47:10Multi-consumer broadcast queue
- 52:20Collector thread implementation
- 55:45Stood atomic necessity
- 58:25Platform differences ARM vs x86
- 1:00:24The necessity of fences
- 1:02:16More performance surprises
- 1:04:51Final optimization cached indexes
- 1:07:34Real world application challenges
- 1:11:10Cache optimization results
- 1:16:25Final caveats and conclusions
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