Proposal for I3C SW Support in Zephyr RTOS
summary
Proposal adds an I3C master driver to Zephyr, claiming backward compatibility with I2C, fewer pins, lower power and up to 33.3 Mbps throughput. Code is Linux-inspired and implements probe, dynamic address assignment at bus init, and concrete read/write command and IRQ handling; hot-join/address-on-connect is not yet supported. Driver behavior and timing/IRQ thresholds are exercised in Zephyr emulation, and the team reports successful transfers and error/retry paths while planning further master features and a slave driver.
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chapters (14)
- 0:00I3C protocol proposal intro
- 1:45What is I3C
- 5:39I3C vs I2C and SPI
- 7:58I3C benefits in embedded
- 9:08I3C SW support in Zephyr
- 9:49I3C driver file structure
- 11:20I3C probe sequence
- 14:57Probe process structures
- 18:07Dynamic address assignment
- 19:34Dynamic address procedures
- 22:49I3C write transfer
- 25:24I3C read transfer
- 27:11I3C in Zephyr summary
- 29:00Q&A on I3C
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