RISC-V IOMMU Architecture Overview
summary
Describes a RISC‑V IOMMU baseline that implements single- and two-stage translation matching SATP/VSATP formats, enforces permission checks, and supports PCIe ATS and MSI routing. Hardware context uses a 24-bit device id and up to 20-bit process id, device-context entries sized 64 bytes, and multi‑level device/process directories pointing to IO-satp page tables. Software interface uses command, fault and page‑request circular queues. A QEMU model and Linux driver are under development as a proof‑of‑concept with spec ratification targeted by year‑end.
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