Introduction to RISC-V Functional Safety Special Interest Group

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SIG‑Safety maps concrete gaps in RISC‑V for certified systems, publishes a public blueprint of the safety processor and is drafting a white paper that lists needed features, gaps and recommendations. Work focuses on multicore timing interference and SoC controls such as cache partitioning and locking, cache deactivation, BIST, ECC, lock‑step redundancy, watchdogs and monitors. Meetings run weekly with industry OEMs, silicon and tooling vendors; participation is tracked (>2 meetings in six months).

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" chapters (8)

1. 0:00Intro
2. 0:13"Functional Safety" in a nutshell (2)
3. 2:59Main Properties for Safety-Critical Syste
4. 4:08What is Functional Safety SIG • A forum to discuss functional safety in a RISC-V context • Primary goals Identily gaps and technical needs for functional safety
5. 5:12Example #1 - Time interference in Multi-Cor • Minimize contention points between independent initiators (cores, DMA masters, etc.)
6. 7:14Example #2 - Hardware Safety Mechanisms
7. 7:54Activity
8. 9:38Engagement Joining