Building an Open HPC Ecosystem

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SIG HPC builds a practical RISC-V path to HPC: a public Jenkins test harness at risk5test.org public Jenkins harness compiles software with GCC and LLVM to show what breaks, and EasyBuild already fixes builds on an Unmatched cluster. A Mellanox ConnectX3 InfiniBand runs with driver tweaks but lacks native RDMA support on current RISC-V kernels. New specs include SV57k virtual memory spec (with SV64 planned) and a Europe lab called SuperV lab at BSC with unmatched clusters, FPGAs and emulators for vector and co‑design experiments.

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" chapters (14)

1. 0:00Introduction to open HPC
2. 1:46Vision for open hardware-software stack
3. 3:07Pragmatic approach to HPC ecosystem
4. 4:09SIG HPC goals and roadmap
5. 7:18HPC software test bed announcement
6. 10:05Testing InfiniBand with RISC-V
7. 12:10ISC 22 BoF session details
8. 12:53Supercomputing 2022 plans
9. 13:34SuperV RISC-V lab at BSC
10. 15:19Hardware options for HPC
11. 16:23European RISC-V ecosystem progress
12. 17:05Timeline of RISC-V adoption in EU
13. 18:51Why HPC is perfect for RISC-V
14. 19:35How to get involved