Preempt-RT Latency Benchmarking of the Cortex-A53 Processor
summary
Benchmarks run on a 4.18 kernel with the PREEMPT_RT patch compare a Zynq UltraScale+ Cortex‑A53 module to a Cortex‑A9 Zed board using cyclictest, CPUsets and stress workloads. cyclictest shows 17 μs max on Cortex‑A53 vs 54 μs on A9. UDP ping‑pong round trip is about 168 μs on A53 (one‑way ≈84 μs) while A9 shows sporadic tails >800 μs. A simulated SPI ADC in PL + DMA engine plus a hardware timer capture yields IIO DMA callback max latency 30 μs.
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chapters (14)
- 0:00Start
- 2:32Why Real-Time Linux?
- 4:53Hardware Setup
- 6:58Kernel
- 8:47Cyclictest Results
- 10:15Cpusets Shielding
- 13:31UDP Ping Pong Test
- 15:28UDP Ping Pong Results
- 17:31Real World Test
- 18:18Industrial Input/Output (110)
- 19:28Hardware Configuration
- 22:55Timer Capture Function
- 25:01Conculsions
- 27:07Future Work
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